1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device of a multilayer metal interconnection structure. Yet more particularly, the present invention relates to a wordline architecture utilizing reduced metallization layers.
2. State of the Art
Memory devices store data in vast arrays of memory cells. Essentially, the cells are located at intersections of wordlines and bitlines with each cell conventionally storing a single bit of data as a logical “1” or a logical “0” and can be individually accessed or addressed. Conventionally, each cell is addressed using two multi-bit numbers. The first multi-bit number, or row address, identifies the row of the memory array in which the memory cell is located. The second multi-bit numeral, or column address, identifies the column of the memory array in which the desired memory cell is located. Each row address/column address combination corresponds to a single memory cell. The row and column addresses are applied to inputs of row and column decoders to access an individual memory cell. Conventionally, row and column decoders are fabricated using programmable logic arrays, wherein these arrays are configured to select desired word and bitlines based on address signals applied to the inputs of the array.
FIG. 1 is a diagram illustrating an arrangement of memory cell regions of a conventional memory device, such as a dynamic random access memory (DRAM) in accordance with a wordline shunt architecture. In FIG. 1, the DRAM includes two memory cell regions, 120 and 122 placed in respective regions on a semiconductor chip. The memory cell regions 120, 122 each have a predefined storage capacity, for example, of 2N total bits. A peripheral circuit 124 is placed in a region adjacent to memory cell regions 120, 122. Peripheral circuit 124 includes a peripheral control circuit (not shown) that controls the operation within memory cell regions 120, 122. By placing the memory cell regions 120, 122 in a plurality of symmetric regions on a semiconductor chip, the length of wordlines and bitlines may be reduced to decrease the time requirement for selection of a memory cell within a memory cell region 120, 122 for the extraction or insertion of data within a respective memory cell.
FIG. 1 is a diagram schematically showing an example of a configuration of memory cell regions 120, 122 wherein each cell region may be configured in a similar arrangement forming smaller subdivided portions of a memory device 100. By way of example, a memory device 100 may be divided into multiple memory cell regions traversed by one or more wordline arrangements 130-144 and further traversed, generally in an opposing direction, by one or more column select lines 150-156. According to the wordline shunt configuration, as presently described, memory device 100 further includes one or more shunt regions 160-164.
Wordline shunt regions 160-164 are regions in which a conductively electrical connection is formed between a highly resistive wordline connected to the gates of corresponding memory cell transistors and a low resistance metal interconnection line 190-204. Interconnection between metal interconnection lines 190-204 with wordlines 170-184 reduces the resistance of wordlines 170-184 thereby enabling a higher speed transmission of a wordline drive signal 210-224 across one or more memory cell regions 120, 122.
FIG. 2 is a schematic showing a configuration of a wordline configured according to a shunt architecture. According to FIG. 2, reference numerals corresponding to a specific wordline arrangement of FIG. 1 are reused for the discussion relating to the current figure. The wordline arrangement 130 includes a wordline drive signal 210 coupled to a wordline driver 230 which is coupled to a low resistivity metal interconnection line 190 which is generally located in parallel to wordline 170. Metal interconnection line 190 and wordline 170 are both coupled to wordline driver 230. Metal interconnection line 190 and wordline 170 are electrically connected in one or more shunt regions 160-164. In each of the memory cell regions 120, 122, the metal interconnection line 190 includes a resistance RM while the wordline 170 has a resistance RP, wherein the wordline is generally comprised of polysilicon which exhibits a much greater resistance than that of a metal-based interconnection line. It is noted herein that when a higher resistance wordline, such as wordline 170, is driven by a wordline driver 230 physically implemented generally at one end of wordline 170, an appreciable propagation delay arises throughout the length of the wordline 170, particularly at a location along the wordline that is farthest from the wordline driver 230. Such a propagation delay reduces the overall maximum speed of the device, and is therefore undesirable.
The propagation delay along the wordline is improved according to the wordline shunt architecture as presently described through the utilization of a metal interconnection line 190 which is provided in parallel with wordline 170 and electrically connected thereto through contacts occurring in one or more shunt regions 160-164. Therefore, since the higher resistance wordline 170 is coupled in parallel with a lower resistance metal interconnection line 190, the overall reduction in resistance enables the wordline signal to propagate more quickly across the length of the wordline 170.
FIG. 3 illustrates a cross-sectional view of a portion of memory device 100 as illustrated with reference to FIG. 1. As illustrated, the wordline shunt architecture is implemented through the use of two layers of metal interconnections, metal 1 and metal 2, and through the use of a polysilicon layer for forming the wordline for the corresponding memory cells.
One alternative to a wordline shunt architecture configuration of a wordline includes a hierarchical wordline architecture utilized to drive a wordline across at least a portion of a memory device at an even higher speed than the afore-described wordline shunt architecture. FIG. 4 is a diagram illustrating the hierarchy wordline architecture. In FIG. 4, a memory device or at least a portion of a memory device 300 includes a memory cell region 320 divided from other memory cell regions by one or more subword driver regions 360, 362. One or more main wordlines 310, 312 are commonly provided to one or more memory cell regions 320 and are further aligned in, for example, a row direction. One or more wordlines 370-384 are provided in each of the memory cell regions 320 corresponding to respective memory cell rows of a memory cell region 320. The wordlines 370-384 are generally comprised of polysilicon which is of a significantly higher resistivity material than a metallization interconnect. In the respective subword driver regions 360, 362, subword drivers 330-344 are provided generally dispersed alternatively on opposing sides of memory cell region 320.
In the hierarchy wordline architecture, each main wordline 310, 312 corresponds to a corresponding plurality of wordlines 370-384. The main wordlines 310, 312 are formed from low resistive metal interconnection lines. The wordlines are constructed in a hierarchical structure including main wordlines driven by a main wordline driver (not shown) and wordlines driven by subword drivers 330-344. Since individual memory cells are not connected to the main wordlines 310, 312, the resistance and capacitance of the main wordlines 310, 312 remain small, enabling a high speed operation of the main wordlines. Furthermore, the wordlines 370-384 are only provided within a corresponding memory cell region which includes a relatively much smaller number of memory cells thereby creating a smaller load to be driven, allowing the wordlines 370-384 to be driven into a selected state at a much higher speed.
FIG. 5 is a schematic diagram specifically showing the configuration of a hierarchical wordline architecture. In FIG. 5, a subword driver 330 commonly drives a wordline 370 into a selected state corresponding to a main wordline 310. The main wordline 310 includes a low resistance RM while the wordline 370 includes a higher resistance RP. As shown, the wordlines are organized in hierarchical architecture including a main wordline 310 and wordline 370 with the main wordline 310 formed of a metal interconnection line with a smaller resistance while the wordline 370 is comprised of a higher resistive polysilicon.
FIG. 6 is a cross-sectional view of a hierarchy wordline architecture. As illustrated, the wordline hierarchy architecture is implemented through the use of two layers of metal interconnections, metal 1 and metal 2, and through the use of a polysilicon layer for forming the wordline for the corresponding memory cells.
In order to increase the operating frequency of a memory device by incorporating a hierarchical wordline architecture, the quantity of memory cells traversed by the wordline is reduced. Such a reduction causes a further partitioning of the memory cell region into ever smaller regions which may create a layout inefficiency within a memory array of a memory device. Furthermore, when a memory device incorporates a wordline shunt architecture, a necessity arises to use an interconnection layer different from the main wordline interconnect and the wordline interconnect for use in forming a shunt. The formation of such a shunt generally results in an increased number of metal interconnection layers. Therefore, there is a need to provide a wordline architecture which provides an adequate access rate to the memory device without further burdening the manufacturing processes to include an additional layer, such as an additional metallization layer.